Procédé et dispositif de test de circuits d'attaque à trois états

Method and apparatus for testing three state drivers

Verfahren und Gerät zur Prüfung von Tri-State-Treibern


In an integrated circuit chip (10) utilizing CMOS technol­ ogy, an embedded data bus (11) is driven by embedded three state drivers (12-15), and the bus is in turn connected to provide a drive signal to embedded receivers and similar logic devices. An embedded threshold detector (19) is provided to detect the occurrence of any invalid data signal (i.e. a non-"0" or a non-"1" signal level) on the data bus. The threshold detector's output signal is connected to off chip terminal means, to thereby enable off chip monitoring of the bus signal. The threshold detector's output signal is also ANDed with the bus sig­ nal, to thereby prevent the application of a potentially destructive invalid bus signal to the receivers and the like. Terminator circuit means provides a known invalid signal state on the bus when the bus is in its high imped­ ance state due to all of the three state drivers being disabled.




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Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    WO-8400834-A1March 01, 1984Western Electric CoMethod and apparatus for bus fault location

NO-Patent Citations (1)

    IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 9, February 1981, pages 4156-4158, New York, US; H.D. SCHNURMANN et al.: "Testing of tri-state driver circuits"

Cited By (0)

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